1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a reset circuit for a timing controller that includes a unit preventing a voltage-induction phenomenon due to Low Voltage Differential Signaling (LVDS).
2. Discussion of the Related Art
Recently, flat panel displays (FPDs) are being developed to have a high frequency and a high resolution for achieving a higher display quality. Among various types of FPDs, liquid crystal display (LCD) devices have been the subject of recent researches. In the LCD devices, since a data signal and a clock signal are transmitted through a transistor-transistor logic (TTL) signal having a high frequency, a voltage level of image signals is shifted to correspond to the high frequency of the TTL signal. The shift of the voltage level causes an electromagnetic interference (EMI) problem. Moreover, since a large number of transmission paths are necessary to transmit the data signal and the clock signal through the TTL signal, a large number of cables and connectors are required to the LCD devices. Accordingly, the data signal and the clock signal are directly or indirectly influenced by an external noise, thereby images may be abnormally displayed. In addition, a number of data transmission bits supported by a graphic controller for achieving a full color high resolution is restricted.
To solve such a problem, a low voltage differential signal (LVDS) specification for an interface between a main body of a computer and an LCD device has been proposed. The LVDS specification is a new data interface standard that is defined in the IEEE 1596.3 standards. It is essentially a signaling method used for a low-voltage and high-speed data transmission. In general, the LVDS technology provides a narrow band high-speed interface between an LCD device mounted in a notebook computer and a graphic controller of a motherboard, or uses a cable to a monitor of a desktop computer.
FIG. 1 is a schematic block diagram showing a connection between a main body of a computer and a liquid crystal display device according to the related art.
In FIG. 1, a graphic card 12 is provided in a main body of a computer as a signal source. The graphic card 12 supplies a color signal of a TTL level including red (R), green (G) and blue (B) signal components, and a plurality of control signals to first and second LVDS transmitting units 14 and 16. To display color images in a line inversion method or a dot inversion method according to a physical characteristic of a liquid crystal, the R, G and B signals are respectively supplied to the first and second LVDS transmitting units 14 and 16 with opposite polarities. A control signal including a horizontal sync signal component, a vertical sync signal component and a data enable (DE) signal component is supplied to the first LVDS transmitting unit 14.
Each signal supplied to the first and second LVDS transmitting units 14 and 16 is converted into an LVDS, and the LVDS is transmitted to a liquid crystal display (LCD) device 60 through a plurality of channels. First and second LVDS receiving units 18 and 20 of the LCD device 60 receive the LVDS transmitted through the plurality of channels. The first and second LVDS receiving units 18 and 20 convert the LVDS into a TTL signal and send the TTL signal to a timing controller 22. The timing controller 22 generates control signals of TTL levels for an LCD module 24 and determines a timing format of the control signals and the R, G and B signals. The control signals and the R, G and B signals in the timing format are supplied to the LCD module 24.
The LCD module 24 includes a source driver (not shown), a gate driver (not shown) and an LCD panel (not shown). The source driver and the gate driver are loaded on a printed circuit board (PCB) and the PCB is connected to the LCD panel. The R, G and B signals and some control signals are applied to the source driver and the other control signals are applied to the gate driver. The LCD panel includes a thin film transistor (TFT) (not shown) in each pixel region. The TFT is turned ON or OFF according to a switching pulse outputted from the gate driver. A data signal from the source driver is applied to the pixel region where the TFT is turned ON and a liquid crystal layer of the pixel region is driven to be transparent.
In FIG. 2, a first electrostatic protection circuit 28 is connected to an LVDS transmitting unit 14 and a second electrostatic protection circuit 28 to an LVDS receiving unit 18 of a timing controller 22. The timing controller 22 includes a reset circuit 30 to enable a specific signal such as source control signals (SSC, SOE, SSP) and gate control signals (GSC, GOE, GSP). The timing controller 22 may include a plurality of LVDS receiving units 18 and a plurality of reset circuits 30. When an input voltage “Vin” (not shown) for the entire circuit is not applied, i.e., a resource voltage of about 3.3 V is not applied to each DVCC node of the electrostatic protection circuit 28 and the reset circuit 30, an LVDS voltage of about 1.4 V (±several hundreds mV) outputted from the LVDS transmitting unit 14 is inputted to the timing controller 22 through the second electrostatic protection circuit 28.
In FIG. 3, a graphical view shows an LVDS voltage outputted from the LVDS transmitting unit when a resource voltage is not applied to each DVCC node of an electrostatic protection circuit and a reset circuit according to the related art.
In FIG. 4, a circuit diagram shows an operation of an electrostatic circuit when an LVDS voltage outputted from the LVDS transmitting unit is inputted to the electrostatic circuit according to the related art. When an LVDS voltage of about 1.4V is inputted to an electrostatic protection circuit, a current flows to a first DVCC node through a forward diode “DF” because a reverse diode “DR” is grounded. Accordingly, the first DVCC node has an induced electrical potential of about 0.3 V to about 0.7 V.
Referring again to FIG. 2, since the first DVCC node of the second electrostatic protection circuit 28 is electrically connected to a second DVCC node of the reset circuit 30, the second DVCC node of the reset circuit 30 also has an induced electrical potential of about 0.3 V to about 0.7 V. When an input voltage “Vin” (not shown) for the entire circuit is applied, i.e., a resource voltage of about 3.3 V is applied to the second DVCC node of the reset circuit 30, a capacitor “C” of the reset circuit 30 is not charged up from 0 V but from about 0.7 V due to the induced electrical potential of about 0.7V by the LVDS voltage of about 1.4 V.
In FIG. 5, a graph represents a GOE signal outputted from a timing controller according to the related art. When the reset circuit 30 (of FIG. 2) enables the source control signals and the gate control signals through the timing controller 22 (of FIG. 2), especially, a GOE (gate operation enable) signal is applied to the gate driver, a duration (GOE mask time) longer than about 16 msec should be obtained for a normal operation of the gate driver. As shown in FIG. 5, however, the GOE signal outputted from the timing controller 22 (of FIG. 2) has a short duration of about 2 msec (indicated with an arrow). The short duration may cause an abnormal operation of the gate driver, thereby the LCD panel may abnormally display images.
In FIG. 6, a graph represents an input voltage and a clock according to the related art, wherein when an input voltage “Vin” is applied to the entire circuit, a clock signal “CLOCK” for a source driver has an undesirable impulse (indicated by the ellipse) causing abnormal images.